Data transmission over cables and wires has enabled much of the economic and technological development over the last few decades. From early electrical telegraph lines by Samuel Morse, to copper cable lines distributing news, entertainment, and high speed internet. Today, the cutting edge of data transmission is in fiber optic communication. Optical fiber is used by many telecommunications companies to transmit telephone, internet, and television signals. Optical communication technology is also commonly used in private and corporate networks, home and commercial theater technology, as well as myriad other sectors.
Due to lower attenuation and interference, optical fiber has large advantages over existing copper wire in long-distance and high-speed applications. However, many challenges still exist in maximizing the data transfer rate over fiber optics. To receive optical data, a clock and data recovery (CDR) circuit is required to reconstruct separate clock and data signals from a single serial data signal.
Many prior art CDR circuits include logic that must run at the same frequency as the received data signal, which makes low-cost and high-speed fiber optic receivers difficult to produce. An incoming optical signal is converted to a corresponding electrical signal using a photodiode. On-off keying (OOK) or amplitude shift keying (ASK) are commonly used to encode data on a carrier wave, but other signal types are used as well.
The electrical signal is converted to binary data by sampling the electrical signal between transitions of the data signal, and the signal is also sampled at the data transitions. The data samples that occur between data transitions are in-phase (I) samples, and the data samples that occur at the transitions are quadrature (Q) samples. In-phase, or data, samples and quadrature, or edge, samples are compared to identify whether a quadrature sample occurred before or after an actual transition of the incoming data signal. The sample clock is adjusted accordingly to stay synchronized with the incoming data signal.
A half-rate phase interpolator (PI) CDR uses multiple samplers and multiple evenly spaced sampling clocks to reduce the clock frequency of CDR logic. However, prior art half-rate CDRs require an external reference clock input which can reduce jitter tolerance when the reference clock input is at an offset frequency compared to the clock signal of the received data signal. The frequency offset can be overcome by adjusting the external reference clock frequency, but then a separate reference clock is required for each CDR receiving data at a different data rate. Even if a group of CDRs is receiving data at the same rate, clock distribution and buffering will use a significant amount of power.